yxyswag

Make Chisel5 generate parameter in Verilog

3

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** I think that it will be greater if chisel5 can add parameter function. In Verilog,...

**Type of issue**: other enhancement **Impact**: API addition (no impact on existing code) **Development Phase**: request **Other information** I have two questions that I have not found these two functions...

``` from mrjob.job import MRJob from mrjob.step import MRStep import re import numpy as np WORD_RE = re.compile(r"[\w']+") class WordCount(MRJob): def mapper(self, _, line): for word in WORD_RE.findall(line): yield (word.lower(),...