yuqi-ali

some question about bus slave Factory

1

While learning SpinalHDL，when using bus slave Factory，I have some questions： In bus slave Factory ，the follow scala code： `val axiLite4Ctrl=new Area { val axiLite4Ctrl=new AxiLite4SlaveFactory(io.axiLite4) axiLite4Ctrl.readAndWrite(pwmGen.enable,0,0,"Pwm Enable bit") axiLite4Ctrl.readAndWrite(pwmGen.dutyCycle,4,documentation ="duty...

Stringread example throws std::bad_alloc

19

stringread]# fletchgen -r names.rb -s memory.srec -l vhdl --sim [INFO ]: Loading RecordBatch(es) from names.rb terminate called after throwing an instance of 'std::bad_alloc' what(): std::bad_alloc

Can you give me an email address？

1

HI My Team Leader is interested in this project. Can you give me your email address? My email address is [email protected] Thanks.

Are there some bugs in clockDomain.waitSampling() API?

10

I have a StreamMonitor Written by myself,the core function is running this function by fork: ``` while (true) { log.info(s"bus_valid:${bus.valid.toBoolean}\tbus_ready:${bus.ready.toBoolean}") if (busValidPtr.toBoolean/*.manager.getLong(busValidPtr.signal)!=0*/) { active.set() if (busReadyPtr.toBoolean/*.manager.getLong(busReadyPtr.signal)!=0*/) { recv(sample()) } }...