ylevhari

I am getting errors that say: %Error-ASSIGNIN: /rdata/dub/verif/ylevhari/verilator_test/fixed_src/dwc_ddrphy_pll.v:899:17: Assigning to input/const variable: 'vp' 899 | .vp({vp,vp}), This is an assignment to an inout signal, which is legal verilog, how can...