xxq

make verilog NUM_CORES=4 gets error

7

### Before start - [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。 - [X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。 - [X]...

In VCS simulation, multi-core simulation of some harts ended prematurely due to incorrect execution of SEQZ instruction

1

### Before start - [X] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。 - [X] I have read the [XiangShan...

amtest -> mp test 多核仿真结果不一致，修改__barrier代码实现后一致了，是为什么？ 这是修改之前的仿真结果：  这是修改后的代码（上面的是原来的，后面的是我写的）以及仿真结果（vcs和verilator完全一致）：  

it should return to the parent directory after updating the submodule.