Icser

The wave reload question of VCS simulation

3

HI ! I meet a question when using the VCS simulation，Here is my question： using "shift + L" in the VCS can reload the wave. However, when I recompile the...

Whole Soc Component like the Vexriscv

6

Hi ! Do you have any plans about implement the the whole soc (with spi，uart) , which can boot the linux simulation and show results from the uart?

Some Riscv-Tests Can't Pass

3

Hi ! When I excute riscv-tests with the config ``` val l = Config.plugins( sideChannels = false, //WARNING, FOR TEST PURPOSES ONLY, turn to false for real stuff