xiaoweish

Wish it helps, https://github.com/riscv-software-src/riscv-tests/tree/master?tab=readme-ov-file#test-virtual-machines https://riscv.org/wp-content/uploads/2015/01/riscv-testing-frameworks-bootcamp-jan2015.pdf

As to this case `rv32mi-csr`, this PR might help. https://github.com/openhwgroup/core-v-verif/pull/2424 [B Standard Extension for Bit Manipulation Instructions](https://drive.google.com/file/d/1SgLoasaBjs5WboQMaU3wpHkjUwV71UZn/view?usp=drive_link) is ratified on April 2024, listed in [Ratified Extensions](https://wiki.riscv.org/display/HOME/Ratified+Extensions)

Hi @JeanRochCoulon, Sorry for missing your comment! Yes, it’s on my task list. I’ll update it once ready! Thank you! Xiaowei

Hi @MikeOpenHWGroup As to step 1 in `How to?` > 1. Add a [debug control virtual peripheral](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/test_programs.html#virtual-peripherals) to the testbench and connect it to the [debug_req_i](https://github.com/openhwgroup/core-v-verif/blob/8dac926e4c7693c52609572b4f8281eec30c9823/cva6/tb/uvmt/cva6_tb_wrapper.sv#L78) input of the core....

Here is my proposed fix: https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L827 ```verilog // -------------------- // Counters // -------------------- cycle_d = cycle_q; instret_d = instret_q; - if (!debug_mode_q) begin + if ( !(debug_mode_q==1'b1 && dcsr_d.stopcount==1'b1) )...

Hi @JeanRochCoulon , Yes, it would be beneficial to incorporate the debug job into CI once [debug_test](https://github.com/openhwgroup/cva6/issues/1364) is implemented. This issue was indeed discovered during the `debug_test`. Once PR https://github.com/openhwgroup/cva6/pull/2293...

Hi @fatimasaleem , Per below link, arch-test support `Zicond` and `zcb` now. https://github.com/riscv-non-isa/riscv-arch-test/blob/dev/CHANGELOG.md ```markdown ## [3.8.3] - 2023-11-30 - Add Zicond ISA extension support ## [3.8.4] - 2023-11-30 - Added...

Hi @jb-brelot-nxp , May I ask if there’s any conclusion on this? Thank you!

Hi @AnouarZajni, Could you please spare some time to review this PR?

Thanks @AnouarZajni ! I removed interrupt agent from this PR and make this change much more atomic, which only contains debug agent.