yuqi

After I write a wavedrom to dispaly reg,the second signal wavdrom can't display normaml ```wavedrom { reg: [ { "name": "0", "bits": 1, "attr": "", "type":6 }, { "name": "0",...

I use cocotb 1.6.2 to test the Bus.driver() ```verilog module dut( input [7:0] data_in_data0, input [7:0] data_in_data1, output logic [7:0] data_out_data0, output logic [7:0] data_out_data1 ); always_comb begin data_out_data0=data_in_data1; data_out_data1=data_in_data0;...