Sergi・セルジ

Also uses libelf instead of manually copied ELF headers.

[BUG] [RISC-V] configMTIMECMP_BASE_ADDRESS (64-bit) stored in 32-bit int

5

**Describe the bug** `configMTIMECMP_BASE_ADDRESS`, which can be a 64-bit address is currently being stored in a 32-bit integer: ``` uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS; ``` GCC port: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/master/portable/GCC/RISC-V/port.c#L94 IAR port:...

CodeGen_MLIR: Add initial MLIR CodeGen

9

Initial implementation. Just a proof-of-concept to show that MLIR generation is possible and quite straightforward. It uses the following MLIR dialects: `arith`, `func`, `memref`, `scf`, `vector`. Future work: - Implement...

At https://github.com/veeresht/CommPy/blob/master/commpy/channelcoding/convcode.py#L546, I see that the bits from the RSC FFs are taken individually and utilized as if they were the message input bits to determine the next branch. However,...

[Draft] Remove polygeist + Bump to LLVM 17

1

On top of @hanchenye's [remove-polygeist](https://github.com/hanchenye/scalehls/compare/remove-polygeist) branch.

STM32_UART: Add Idle line detection and interrupt

1

Useful when we don't know a-priori how many bytes we will receive, yet we want to get an interrupt as soon as we see 1 idle UART frame so that...

This should fix the problem certain games have when running with EmuNAND.

Added CIA and CCI Makefile rules

1

Added CIA and CCI Makefile rules Updated to compile with the latest libctru version

Draft: DekoCompiler: Add OutputDkshToMemory method to output shader to memory

2

This will allow using UAM as a library (I'll add support for it in a future PR). Marked as a draft because I think it would be better to add...

[SCFToCalyx] Add support for sequential read MemRefType memories

8

If a FuncOp argument is of `MemRefType` and has the boolean attribute `calyx.sequential_reads` set to true, consider the read accesses to that memory as sequential, which adds a "read_en" signal...