Simon Southwell

Results 4 repositories owned by Simon Southwell

pcievhost

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PCIe (1.0a to 2.0) Virtual host model for verilog

riscV

27
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12
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Open source ISS and logic RISC-V 32 bit project

vproc

46
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9
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Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

mem_model

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High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model