Simon Southwell
Results
4
repositories owned by
Simon Southwell
pcievhost
81
Stars
21
Forks
Watchers
PCIe (1.0a to 2.0) Virtual host model for verilog
riscV
27
Stars
12
Forks
Watchers
Open source ISS and logic RISC-V 32 bit project
vproc
46
Stars
9
Forks
Watchers
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
mem_model
18
Stars
1
Forks
Watchers
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model