wxrdnx
wxrdnx
> Very nice! Thanks a lot! > > How did you generate the `InsnOp.inc` table? Did you use the legacy scripts or Auto-Sync? In the last case: are there any...
> We have to trigger the CI every time when you push (because we want to stay within the CI ranges, which are free). So I'd suggest you try to...
New change: 1. Fix incorrect operands for the csr instruction and the cs.w (and its variants) instruction. 2. Add Python binding 3. Add new test cases for M,A,F,D,C instructions
This error is caused by an insufficient number of operands in `sfence.vma`. Similar bug occurs in `fence`. Both should be fixed now.
Hi, May I ask what is the purpose of `test/cs_detail/issue.cs`? What test cases should I add to it? Thank you!
Added tests in`test/cs_detail/issue.cs` Also rebased to `next`
I've added support for RISC-V CODGEN_ARCH. I've tested cross compiling x64 codegen on RISC-V machine and cross compiling RISC-V codegen on x64 machine. Both worked fine. See #1972
This issue exists before my commit I got the same result from commit `9c5b48b5` (The commit before my pr is merged) ``` $ cstool -d riscv64 67800000 0 67 80...
> @wxrdnx, a more descriptive title for the PR and the commit would be `add RISC-V instruction mnemonics and registers`. You can change the PR title with the `edit` button,...
> Ah, sorry. I didn't look at this before merging #1842. You'll need to move the ROSE register stuff into dataflowAPI. Let me know if you have any questions. Got...