Wilson Snyder
Wilson Snyder
#1870 points out some tests that were added that are not consistent/complete designs. I'd like to suggest a new policy that before any new tests be accepted, failures against every...
The projf-explore tests were recently added. Almost none of them are runnable on a simulator (verilator/icarus) as there are missing modules. These need to be fixed to "fairly" grade tools...
- Can you consider renaming "module top" in your tests to "module t"? This makes us able to run your tests under the Verilator test framework without changes. (We can...
Some suggestions to make debugging tests easier using the runner: - [ ] When creating logs/.. add a symlink to the .v input files, so a .log is adjacent to...
Maybe I missed a feature but would like to see tracking of expected results. I'd like to encourage use of this project for continuous integration of Verilator, but to do...
Please consider improving the README with: - How to use RUNNERS= to run just one runner - I figured it out but would be nice to document it. - How...
This fixes one of the easier UNOPTFLAT warnings from Verilator. Some bits of dccm_wr_data_lo were used to generate other bits of dccm_wr_data_lo. Using a temporary fixes this. This should be...
Towards UVM support, add support for the process class described in IEEE. See the test_regress/t_process.pl test (which currently fails). Note there are comments in there; some features are not needed...
Traces with --timing sometimes have many timing events that do not result in any signals changing, e.g. t_timing_osc. This results in a bunch of timestamps in the VSD/FST that are...
IEEE plans on approving 1800-2023 early December, with publication around Feb/Mar. I have several related pulls ready in a private area. Currently the draft standard is only available to certain...