Wilson Snyder
Wilson Snyder
Verilator's test driver has a separate check that the hierarchy of signals remains the same, because that feature was not in vcddiff. https://github.com/verilator/verilator/blob/5b410e9331b1543889287a965d0ea016d9a6b6d7/test_regress/driver.py#L2377 It would be good to support that...
Please consider adding to verible-format-verilog support for ifdef/ifndef/elsif formatting, similar to [Verilog-mode verilog-indent-level-directives](https://veripool.org/verilog-mode/help/#verilog-indent-level-directive) Presumably an option is needed to set indent level, defaulting to 0 for old behavior. E.g. should...
**Describe the bug** Currently `verilog_format: off` can be used to stop formatting on a region, but unlike e.g. `clang_format off` this does not turn off the lexer. This means that...
Currently using `-lint-only` does not imply `--timing` nor `--no-timing` and on any timing construct a NOTIMING warning will ask the user to be more specific. Given timing is now more...
The below, rewritten from UVM tests/10resources/90Mantis/4666_no_process results in a compile-time error: ``` In file included from Vt_0__ALL.cpp:4: Vt_0___024root__0.cpp: In function â\200\230VlCoroutine Vt_0___024root___eval_initial__TOP__Vtiming__0(Vt_0___024root*, VlProcessRef)â\200\231: Vt_0___024root__0.cpp:25:1: error: no return statement in function...
The following rewritten from UVM tests/05components/50in_order/20int gives a false Verilation error: ``` %Error: t/t_0.v:16:43: Reference to 'T' type would form a recursive definition 16 | type comp_type = uvm_built_in_comp#(T) |...
On current git master: ``` module t; class uvm_reg_field; rand int m_value; endclass class reg_class; rand int m_value; rand uvm_reg_field _dummy; constraint _dummy_is_reg {_dummy.m_value == m_value;} endclass class block_class; rand...
chapter-16/16.2--assert0-uvm.sv broke recently in sv-test (https://chipsalliance.github.io/sv-tests-results/) @gezalore this bisected to (#6613) 287fdb73129b25c4d55b4d4159d9597b2e11d805 You can run on a sv-test checkout with roughly: ``` export VERILATOR_ROOT= export PATH=$VERILATOR_ROOT/bin:~/.local/bin:$V4/bin:$PATH export OUT_DIR=`pwd`/out export TESTS_DIR=`pwd`/tests...
The sv-tests easyUVM test is currently failing with this message: ``` %Error-UNSUPPORTED: sv-tests/third_party/tests/easyUVM/driver.sv:14:64: Unsupported: Write to virtual interface in if condition : ... note: In instance '$unit::driver' ``` This can...
SweRV C++ output has a bunch of code like this ``` a = a & 0xfffffff0 | something; a = a & 0xffffff0f | something_else; ... a = a &...