wsipak

The problem is described here: https://github.com/antmicro/yosys-systemverilog/issues/1043 We've observed that even though this integer is mishandled: ``` assign a = 7698294523898761276; ``` Integers written as based literal constants with the same...

line length rule: add a parameter to check comments

3

This addresses https://github.com/chipsalliance/verible/issues/941 There's a new parameter ~~`allow_comments`~~ `ignore_comments`. When it's set to `false`, exceeding the line length limit in comments won't be forgiven. The default value is `true`, so...

WIP follow-up to (and based on) https://github.com/chipsalliance/yosys-f4pga-plugins/pull/521 I think this might be fixed by https://github.com/chipsalliance/yosys-f4pga-plugins/pull/533 and not needed anymore. Input: ``` typedef logic [3:0][7:0] my_struct_packed_t; module single_range_dot_access ( input my_struct_packed_t...

This tests a case that we've encountered in BlackParrot.

In response to https://github.com/chipsalliance/yosys-f4pga-plugins/pull/391#pullrequestreview-1159636179 I'm adding tests for decimal numbers of varied widths. Please note that the PR mentioned above is supposed to handle decimals up to 64 bits, and...

test specifying privilege modes in simulation in riscv-dv

1

This is a draft to test changes in riscv-dv https://github.com/chipsalliance/riscv-dv/pull/984

Currently we're using the default settings of privilege modes in ISS tools. Whisper needs a 'u' in the ISA string for the User mode to be enabled. Spike, on the...