Will Whang

You might want to double-check the connection between SX1257 and SX1301/1308 Moreover, make sure that the 32Mhz TCXO clock is running, and the power is stable (Note: util_spi_stress doesn't really...

OSC2 should be TCXO and package size should be 3.2mm x 2.5mm, and OSC1 should be 2.0mm x 2.5mm. I use SiTime's product for the hight speed 133Mhz 2025 OSC....

Just to note that the OSC size of the reference design is bigger than the Osc on the RPI-Zero version. There isn't much space on the RPI-Zero version for me...

No, it won't support LBT since it needs a FPGA + SX1278 to scan the channel for LBT. Note that if anyone have the ref V1.5 design sch, I'm willing...

Reopen this issue because it is on my todo list... Hope some day I'm able to implement LBT.

Almost, but you can't, because it is a multi layer board. I'm hoping to reverse by reversing the FPGA bitstream, but I can't read verilog......

@piratfm That was awesome! I'm recently doing other projects that uses ICE5LP1K-SG48 (a.k.a learning verilog), so I also have some chip and boards :D I'm glad that I left a...

Just adding comment that it is working - The board file released is the same as the one I sold on Tindle. Also note that I have another board https://github.com/will127534/LoRa-GW-FeatherWing...

IMAO, I think you need to change the DC-DC and LDO parts anyway because of the silicon shortages. And it should be easy on this project because the board is...

@Brat0x2 Yes it is, SX1308 consume about 0.6A, which means it takes about 1W I did measure about 55~60 Degrees on the SX1308, barely touchable...