Emil J
Emil J
I'd like to have two subfigures side-by-side. I'm using the pandoc-crossref filter method of subfigures. I tried turning them into a subsubfigure, and also the column layout method as described...
### Description Yosys has functionality for subcircuit matching and replacing with modules, which can be instances of standard cells. An example of such a map file is in Yosys at...
### Description As a use case, with small designs, the global placer often crashes. This is meant to be remedied by the `PL_RANDOM_INITIAL_PLACEMENT` option. However, this produces a random initial...
When printf (implemented with HTIF) is used in an executable run with spike, the printed text can not be redirected. As an example, `spike --isa=RV32GC whatever > /dev/null 2>&1` still...
#225 except -T behaves just fine with clang so we don't have to mess with that. Also renamed references to GCC to CC
But I already solved it by using the system timer to lock it to 20Hz! I just can't do a pull request because it's on Gitlab. Consider this issue a...
### Describe the bug When building gcd, RCX at end of flow fails like so: ``` [INFO RCX-0436] RC segment generation gcd (max_merge_res 50.0) ... [INFO RCX-0040] Final 1824 rc...
- remove preprocessLib.py - yosys-abc accepts user-defined attribute `original_pin` used in Liberty file pin declarations of cells it actually uses to map to even if `original_pin` is not defined as...
This PR shows possible usage of the yosys clockgate command to reduce area
The main idea is that if you use yosys `clockgate` to map ICGs to `OPENROAD_CLKGATE`, you need a blackbox to be present, which is missing at that time since currently...