Catherine
Catherine
@RobertBaruch Have you tried my suggestion with the Yosys script?
The reason I'm asking is because your `_initialize` hack will never be added upstream, but my suggestion might, since it is trivial to do while emitting RTLIL. If you actually...
> I'd rather add something to the Python code than something to the sby if I can. Right, I see. Since this is an issue asking for nmigen improvements, I'm...
Okay, I see what you mean: my `reset_less` proposal would solve some but not all of your use cases. We should probably discuss this in more detail when working on...
Yep, this is a known pysim issue that requires reworking the way memories are translated.
Interesting, I thought this would work on 3.7 (https://bugs.python.org/issue31113) but it doesn't.
Yep, this is planned with the next round of simulator improvements. I'm not sure if replacing `Instance`s with simulation models is the best way to address your specific problem (it...
> For my specifc problem it would be helpful to drive `Instance` io's from the simulator (for example to initiate AXI reads / writes coming from the `PS7`) and being...
> (or disconnect them, so the signals connected to the ports can be driven directly) That's the same thing. Toplevel ports currently are treated as disconnected.
> How? Can you describe an example of what you want to do with a PLL?