Catherine
Catherine
Are you sure this is issue is actually present? The `IBUF_LOW_PWR` attribute, when applied as a parameter to the `IBUFDS` cell in your design, does not change the bitstream whether...
> Could it be that the nMigen comment is wrong? Or is the error in the Lattice documentation? If you try to synthesize a design with the pins assigned as...
> Swapping pin names now could lead to confusion with existing addons/documents/code. OTOH, getting a placement error with the names from the schematics will lead to confusion too. Fix it....
Yes, the labels of course.
See also #228.
What I think we should do is to recommend using the inactive edge of a clock domain for testbench logic. This is actually already the recommended way to use CXXRTL,...
There is a partial solution to issue (1) in a [branch](https://github.com/nmigen/nmigen/tree/sim-bench-processes). We discussed issue (2) on IRC and it is possible that nothing needs to be done there because if...
Thanks for the PR. It will likely take a while to merge this because the new applet doesn't quite follow the conventions in the other applets, and I'd like all...
I actually have a partial implementation stashed somewhere. One day I'll get around to finishing it.
Reasonable. I think we might want to wait until there's a Yosys release, because we can't shim over the lack of `$divfloor` in older Yosys in `back.verilog`, like we do...