Catherine
Catherine
I mean that if you swap them in the Verilog output the behavior will be the same.
Amaranth does not guarantee that any one of an equivalent set of names will end up as a `reg` when you synchronously assign to it, only that one of them...
Yeah, I would say it should be.
> * The AXI interface is based on channels which work similarly to amaranth streams, so maybe they could be reused. I do believe that the Amaranth AXI implementation should...
@jorolf I suggest finding some time to discuss this proposal in a more synchronous way (text or voice), will you be available? Note that formally speaking, the maintainer of Amaranth...
You should be able to use [Pershing](http://sigtbd.csail.mit.edu/pubs/2016/paper4.pdf) to add redstone P&R support. If it is feasible to provide ongoing support for, I would consider having it in-tree. [V2MC](https://github.com/Kenny2github/V2MC) seems to...
It doesn't seem like anybody's going to actively work on this any time soon, so closing.
A tooltip would be an improvement, but is there a reason not to add this information permanently? It's essential to correlating variable names to assembly and stack layout, and is...
Brilliant, really excited to try it out :D
I'm on 5.1.7873-test and I don't see the hamburger menu, where is it?