Stefan Wallentowitz

Ah, right, I think I also tracked it down here: https://github.com/freechipsproject/chisel3/blame/e564fff139768e6a232d118ec7155ecf080f1bc4/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala#L46 which should probably be with the quotation marks, right?

Sorry, I cannot reproduce the issue. I just did a clean checkout of the `minion-v0.4` branch and it worked as expected. Which distribution are you using? Anything else you tried...

Hi, I observed the same. This somehow got reactivated, it is the printf-style debug output of the rocket core. It tells you which instructions finished. As no software is loaded,...

Hi, are you sure the opensocdebug python bindings are in your `PYTHONPATH`? About the UART the baudrate is not the issue, because the module actually just ignores it. It is...

Oh, I think there is a misunderstanding. Its now a full blown bootloader, like coreboot or so, but just extending the current `boot.c`.

We also need the size, that is currently missing. Created this issue because I don't want to change this last minute before the release now.

Hi, it is defined in `or1k-sprs.h`. Please include that one. I will soon update the documentation or the source code accordingly. Cheers, Stefan

Definitely something we should add. Problem for is I don't have the board for testing. I could set up everything and compile. Could you help with testing?

As discussed, separated the whitespace fix. Trailing whitespaces will most probably be a permanent pain point in the future as many developer setups (git and editor) will fix those on...

Moved the whitespace fix to #4