Stefan Wallentowitz comments

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                                            Stefan Wallentowitz

Systems: Configurable system with compute tiles only

Still some minor fixes coming in (FPGA still not tested), but overall thats how it is supposed to look. The extension stuff is skipped, lets delay host tile to the...

Systems: Configurable system with compute tiles only

Thanks @imphil, force pushed the fixed commits

Setup time violation @ 100 MHz starting at noc_buffer.out_valid

Hi, I am not fully sure if it is covered by my patch set. Anyhow, lets revisit it once my stuff is merged. Cheers

Reduce number of control sets in 2x2 CCCC Nexys4 DDR design

Thanks for opening that one. I agree that this is an issue and read similar indications over the last weeks.

Evaluate Kactus2 to create structural Verilog modules

I like the idea and contrary to our prior approaches using IP-XACT and Kactus seems more solid. One of the issues I could think about is parameterization, but lets see.

Create documentation library

My original idea was that the "Hardware Developer Documentation" is part of the reference manual and the "Software developer documentation" goes largely into API. Anyhow, I am flexible in the...

Build a platform with a host tile

- [x] Add UART (OSD dem_uart) to compute_tile and make it configurable (turns CT into HT) - [x] Demonstrate with system_2x2_hccc in simulation - [x] Demonstrate with system_2x2_hccc on Nexys4

Build a platform with a host tile

Please find that in branch `host-tile`

Avoid deadlocks caused by packets exceeding the MP buffer size

This parameter should be read by the software from the network adapter as suggested above.

Provide tile-specific configuration

I am a bit undecided on that topic, but open for all solutions. Here are my base thoughts: - The majority of tiles are compute tiles, *but* in future those...