Vojtěch Vrba
Vojtěch Vrba
Hello, I am currently trying that, it seems the FPGA manages to write to the SDRAM. I slightly extended the example SystemVerilog component for QSYS. I am able to watch...
So I have already figured it out - without custom QSYS component. I use External Bus to Avalon Bridge with Address Span Extender (otherwise the External Bus' max address range...
The HPS doesn't have to allocate anything. In fact the HPS must avoid conflict when accessing the part of the SDRAM accessed by the fabric, so the parameter `mem=512M` in...
@Andy2No Well, depending on your requirements, you may prefer STM32G4 MCUs over FPGAs - these MCUs have rich analog peripherals (multiple ADCs and DACs) which can be served using internal...
Same issue here... the `ks_asm` method in Python throws exception with constantly `count = 0`, so it is impossible to trace back the ASM line where the error occurs. Any...
I am sorry but I have no experience with Azure. If the content you are accessing requires login and you don't have username and password, how does the login process...