Venkat Rangan

@roman65536 , are you able to share what fiddling you did? I tried this on my UPduino and I get nothing on my console... I have heard that the RAM...

I see the same issue...

Hello, this is a show stopper bug for me too :( Wishbone gets taken over as the ACK is the wrong polarity. Please merge to baseline when possible so we...

A related reference is the core of the address incrementer for the FuseSoC Wishbone system [here](https://github.com/fusesoc/wb_common/blob/f17eeb1db43e78e5cde8e41506967ccb2d38c4cb/wb_common.v#L41). [This line](https://github.com/fusesoc/wb_common/blob/f17eeb1db43e78e5cde8e41506967ccb2d38c4cb/wb_common.v#L62) to me implies that the Wishbone address is byte oriented in the...

I started down this path as well a little while back :) I quickly came to the conclusion that messing with the hot metal box transmitter thingie is a non-starter...

[CADDX Nebula pro vista](https://www.amazon.com/dp/B0B98TRSBV?psc=1&ref=ppx_yo2ov_dt_b_product_details)

For some reason, the discord link you posted doesnt lead me anywhere. I am experienced with Lattice FPGA's and CSI and can look into the feasibility, heres the project I'm...