Vanessa McHale comments

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                                            Vanessa McHale

Vivado test infrastructure fails on Parameters

Same thing happening here? :( https://gitlab.com/clash-lang/clash-compiler/-/jobs/2704503129 Notably, only three out of the four tests trip this up.

Vivado test infrastructure fails on Parameters

Ok, I've gotten further figuring this out. I think that something trips up when the `testBench` bit is not monomorphic - `mkTestBench x` does not work, but `testBench` does. My...

Vivado test infrastructure fails on Parameters

``` set_property top_lib {#{entity}} [current_fileset -sim] ``` fixes VHDL but breaks Verilog in the process.

Add Xilinx dual clock FIFO primitive to `clash-cores`

Oh fair! I will get on that.

Add Xilinx dual clock FIFO primitive to `clash-cores`

Ok just pushed those two. It now tests that ordering remains upon overflow, and it tests that the simulation completes when it underflows, that is, the DcFifo doesn't depend on...

Add Xilinx dual clock FIFO primitive to `clash-cores`

What I have now is inelegant - it has multiple modules since I can't simulate multiple top-level entities in vivado. This is because of https://github.com/clash-lang/clash-compiler/issues/2264 (which I would like to...

Add Xilinx dual clock FIFO primitive to `clash-cores`

This depends on my hack [here](https://github.com/clash-lang/clash-compiler/issues/2266#issuecomment-1180467617), but now has the thorough tests (RTL)

Add Xilinx dual clock FIFO primitive to `clash-cores`

Ok, the RTL tests: - Test of different (and same) clock domains, read>write and write>read. - Test that nothing goes "backwards" even if we write when the FIFO is full....

Add Xilinx dual clock FIFO primitive to `clash-cores`

@DigitalBrains1 sorry about the line-length :grimacing:, I've got a script to pinpoint things now

Add Xilinx dual clock FIFO primitive to `clash-cores`

Thank you! I've cherry-picked that commit.