vladisslav2011
vladisslav2011
Hello. I have faced this issue too using HackRF in realtime configuration. My config: ``` [GNSS-SDR] ;######### GLOBAL OPTIONS ################## GNSS-SDR.internal_fs_sps=10000000 ;######### SIGNAL_SOURCE CONFIG ############ SignalSource.implementation=Osmosdr_Signal_Source SignalSource.item_type=gr_complex SignalSource.sampling_frequency=10000000 SignalSource.freq=1602000000 ;SignalSource.freq=100000000...
> Hi, can you also look into #415? It would be better to not copy-paste, but to adapt existing code to do syndrome calculation and error correction. And, I think,...
Re-run the CI, please. It's not failing in my repo: https://github.com/vladisslav2011/gnss-sdr/runs/7294814271?check_suite_focus=true
@ZaquL Hamming code can detect 2-bit errors and correct 1-bit error or detect up to 3-bit (and hopefully more) errors if we decide to skip correction and reject all words...
> We already reject all cases https://github.com/gnss-sdr/gnss-sdr/blob/next/src/core/system_parameters/glonass_gnav_navigation_message.cc#L125-L129 We are accepting bad words now... > Because there is a crypto bottleneck somehwere At least BCH decoder is correct. I think, we...
> No, we were accepting bad words before [ec3c868](https://github.com/gnss-sdr/gnss-sdr/commit/ec3c8686250c515303f85b4b741b0ddd6551b7b2). Agree. It's really bad code as I did not understand it without re-reading it multiple times. Now I think, that rewriting...
volk-gnsssdr-macos-xcode CI fails again here, but not in my account. I don't know, what to do in situation like this...
This config works to me. [gps5.txt](https://github.com/gnss-sdr/gnss-sdr/files/8817579/gps5.txt) But not every GPS satellite caries L5 payload. It may be possible, that you will not get 4+ satellites in good positions to get...
Your config file does not look correct. 1. According to NTlab1065 datasheet, the maximum sampling rate at L2 is about 77MHz, but your setting is 99.375MHz. That's wrong. Are you...
OK. If you have tuned PLL-A to somewhere between Glonass and GPS L1, then it may be possible to choose PLL-A as ADC clock source and get 99.375MHz clock. It...