veryl
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veryl-lang
Veryl: A Modern Hardware Description Language
Add runner for [Metrics DSim](https://www.metrics.ca/product).
Currently, Veryl generates invalid SV code if a `parameter` value is given to a generics argument. For example:  Parameter values are not resolved when generating SV code so Veryl...
Multiple assignment by partial assignment is not checked yet like below. This is because it requires parameter evaluation. ``` assign a[0] = 1; assign a[0] = 0; assign a[0] =...
Now type parameter overriding by built-in types is syntax error. ```systemverilog module ModuleA { inst u: ModuleB #( p: logic, ); } ``` This is because `InstParameterItem` can take `Expression`...
```sv module main ( clk: input clock, rst: input reset ) { var r : logic; always_ff{ if_reset { for i : u32 in 0..32{ r[i] = i; } }...
```sv module ModuleA { let a: logic = case 0 { A: 0, B, C: 0, default: 0, }; } ``` ↓ veryl fmt ```sv module ModuleA { let a:...
version: https://github.com/veryl-lang/veryl/commit/978fdb0ab7453bf206e3c6a381eca7c5f5fe678c top.veryl ```sv import pkg::*; module Top { inst m : myif::; } ``` pkg.veryl ```sv package pkg { const XLEN :u32 = 32; } ``` myif.veryl ```sv interface...
This feature is a syntax sugar for array iteration using `for` loop. If one iterator is given then it shows iterated value. ```systemverilog var foo: logic; var bar: logic; bar...
```sv module Top #( param param_type : type = logic, ) { type type_type = logic; struct struct_type { a: logic, } inst m: ModuleA #( T1: param_type, // ok...