Torsten Reuschel

> Looks like you need to rebase before I can test CI. Indeed. Sorry about the hold-up. I finally managed the intended rebase. Please note that this commit has been...

Are there any updates on the end of CI? Still waiting for this PR (or equivalently #1794) to be confirmed for merge.

> @unbtorsten - Can you rebase this onto master so that the GitHub Action CI (which replaces kokoro) runs here? Done

Is CI still broken? How can we move forward with this?

Why not use something like argparse, cf. https://docs.python.org/3/library/argparse.html?

First of all, thank you for this amazing core! I, too, struggle with the documentation. Hence my question that relates to the OP: > My recommendation is to take a...

> Hi, sorry for bother you, but i'm asking myself if you can help me with that. I need to send custom data trough ethernet using UDP and, because i'm...

This is where the the default loopback is implemented: https://github.com/unbtorsten/verilog-ethernet/blob/master/example/Genesys2/fpga_rgmii/rtl/fpga_core.v#L240-L280 (The examples for other boards will be similar, YMMV) The outbound data is wired up here: https://github.com/unbtorsten/verilog-ethernet/blob/master/example/Genesys2/fpga_rgmii/rtl/fpga_core.v#L270-L274

Hi and sorry for not replying earlier. I second Alex' diagnosis of the previous issue with header/payload not being aligned. From what I see in your postings, you have not...

> Thank you for the reply @unbtorsten. I have connected `tx_fifo_udp_payload_axis_tready` to my custom data generation IP which is currently giving constant HIGH to this signal, [...] If I understand...