rv64uv-p-amoadd_w bug

[abejgonzalez]

Chipyard/dev found a bug in running asm tests with Hwacha on Rocket.

https://circleci.com/gh/ucb-bar/chipyard/2056?utm_campaign=vcs-integration-link&utm_medium=referral&utm_source=github-build-link

[jerryz123]

Hwacha does atomics in the L2. If you aren't building with the L2, the AMO tests should fail.

[colinschmidt]

I think we can now fix this with an AtomicAutomata that will do nothing if some outer manager supports them (i.e. if there is an L2).

[abejgonzalez]

That sounds fine with me.

[Ravenwater]

I am running into atomics failures with the Hwacha L2 config as well:

mkdir -p /home/theodore/dev/clones/chipyard/sims/verilator/output/example.HwachaL2Config
ln -fs /home/theodore/dev/clones/chipyard/esp-tools-install/riscv64-unknown-elf/share/riscv-tests/isa/rv64uv-vp-amoor_w /home/theodore/dev/clones/chipyard/sims/verilator/output/example.HwachaL2Config/rv64uv-vp-amoor_w
(set -o pipefail && /home/theodore/dev/clones/chipyard/sims/verilator/simulator-example-HwachaL2Config  +max-cycles=10000000 +verbose  /home/theodore/dev/clones/chipyard/sims/verilator/output/example.HwachaL2Config/rv64uv-vp-amoor_w 3>&1 1>&2 2>&3 | spike-dasm > /home/theodore/dev/clones/chipyard/sims/verilator/output/example.HwachaL2Config/rv64uv-vp-amoor_w.out)
[194040] %Error: example.HwachaL2Config.top.v:324950: Assertion failed in TOP.TestHarness.TestHarness.tile.hwacha.vus.vxuInst.dccInst.vluInst
%Error: /home/theodore/dev/clones/chipyard/sims/verilator/generated-src/example.HwachaL2Config/example.HwachaL2Config.top.v:324950: Verilog $stop
Aborting...
/home/theodore/dev/clones/chipyard/common.mk:111: recipe for target '/home/theodore/dev/clones/chipyard/sims/verilator/output/example.HwachaL2Config/rv64uv-vp-amoor_w.out' failed

C0:     154711 [0] pc=[000000000000407c] W[r 0=0000000000004078][0] R[r10=0000000000004078] R[r16=00000000000040ef] inst=[0305282b] custom1.rs1 (args unknown)
H: [0] pc=[547d3a05f0] SW[r196=000000007d3a05f0][0] SR[r 98=2cad5d873cc24fcc] SR[r 71=000000007d3a05f0] inst=[3300320c5a232669] c.addiw a2, 26
C0:     154712 [0] pc=[000000000000407c] W[r 0=0000000000004078][0] R[r10=0000000000004078] R[r16=00000000000040ef] inst=[0305282b] custom1.rs1 (args unknown)
H: [0] pc=[547d3a05f0] SW[r  0=000000007d3a05f0][0] SR[r  0=2cad5d873cc24fcc] SR[r  0=000000007d3a05f0] inst=[3300320c5a232669] c.addiw a2, 26
C0:     154713 [0] pc=[000000000000407c] W[r 0=0000000000004078][0] R[r10=0000000000004078] R[r16=00000000000040ef] inst=[0305282b] custom1.rs1 (args unknown)
H: [0] pc=[547d3a05f0] SW[r  2=000000007d3a05f0][0] SR[r  2=2cad5d873cc24fcc] SR[r  0=000000007d3a05f0] inst=[3300320c5a232669] c.addiw a2, 26
H: write_prf 0 0   0 0 1
H: write_prf 0 0   0 1 1
Assertion failed: VLU: non-zero quiescent bias_tail
    at dcc-mem.scala:505 assert(bias_tail === SInt(0), "VLU: non-zero quiescent bias_tail")