Correct initialization in LaneCtrl

Open donggyukim opened this issue 6 years ago • 2 comments

This seems to be necessary.

Feb 26 '19 20:02 donggyukim

How long did you hold reset? Pipelined reset in Hwacha is a bit longer than in Rocket.

Feb 26 '19 20:02 colinschmidt

5 cycles. But, I believe this is due to: https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/lane-ctrl.scala#L66

If its value is greater than nSlices, it'll unexpectedly fire.

I actually got this assertion at the beginning of simulation:

Assertion failed: check sreg sched logic vqu_0
    at lane.scala:184 assert(!uop.valid || !uop.bits.sreg(i) || ctrl.io.uop.sreg(ri).valid, "check sreg sched logic "+name+"_"+i)

Feb 26 '19 20:02 donggyukim