hwacha
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Microarchitecture implementation of the decoupled vector-fetch accelerator
Hwacha uses `FPInput/FPResult` in `scalar-fpu-interface.scala`, but `io.cp_resp.valid` never set to `true`, it is not connected to `divSqrt_wen` only to `mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint`. This means that all operations with...
The website linked from this repository's About section seems unavailable now. Removing or updating the link to a UCB EECS tech report or whatever would be great.
We wanted to start some research with the hwacha architecture. Is RISC-V vector extensions support in the cards at this moment? If yes, when do you plan to get to...
Hello, I am currently optimizing a code to run using Hwacha and I have this scenario. for(int i = 0; i < n; i++){ out[i] = vec1[i]* const_float / vec2[i]...
I was wondering if this project could be used to accelerate [xtensor](https://github.com/xtensor-stack/xtensor) code. Would the compiler be able to auto-vectorize?
currently WithConfPrec is set to off by default, so there is no difference between the HOV Configs and LOV Configs. It seems that the ConfPrec can work now. maybe it...
how to specify the number of shared units (for example the FMA units) in a lane?
hi we want to add an reduction instruction to sum all the element of a vector and the result is placed in a shared register. You can see the similar...
