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Manual clock gating
We'll leave manual clock gating until we need/want it.
Originally posted by @colinschmidt in https://github.com/ucb-bar/hammer/pull/362#issuecomment-485517427
What do you mean by "Manual clock gating"? Generally the next step up from #362 is to do architectural clock gating, which is when you instantiate the clock gating cells in RTL. The technique from #362 tries to opportunistically find registers that it can prove won't update and then skip clock cycles there with a tool-generated control signal.
Yeah we just need to make sure things like this: https://github.com/freechipsproject/rocket-chip/blob/a457f658a7104e2d8e50b003e3a350c72e18df13/src/main/scala/rocket/RocketCore.scala#L105 work correctly. I believe there shouldn't be anything aside maybe some mapping to a tech cell?
Yeah I was thinking an API that lets you do FIRRTL Annotation -> Hammer IR -> Hammer maps something like the above to a tech-specific clock gating cell (which I believe is what Colin is also getting at).
This might be more than "low priority" in that case, if we want to use rocket's clock-gating features.
Also if freechipsproject/firrtl#1017 ever happens this might no longer be needed due to native firrtl support
Well, in that case we'll need a corresponding Hammer pass to extract the FIRRTL primitive and replace it with a greybox. e.g. certain CAD tool vendors may have their own syntax to force something to be synthesized/mapped in a certain way, and clock-related things often need special attention.
Maybe. The tools should be able to map RTL descriptions of clock latches, but we may want to do it manually anyway. I think we'll need to play with it.