Gemmini implementation: misunderstanding of Serial_tl port usage

[deykid]

Hi everyone,

I am looking to implement Gemmini on an FPGA (zcu102). I have generated a project with a rocket core to host Gemmini, but I have some questions. I wonder about the use of serial_tl ports in my case. Indeed, I looked at the signals through GTK Wave and I saw that serial_tl ports are used. However, I am not able to find exactly in the test bench where the sent data are defined. Also, I found some explanations about tilelink or SerDes in the chipyard documentation, but I'm not sure what these ports are used for in my case.

• https://github.com/ucb-bar/chipyard/blob/main/docs/Advanced-Concepts/Chip-Communication.rst
• https://github.com/ucb-bar/chipyard/blob/main/docs/Generators/TestChipIP.rst

Could someone give me more explanation about how these ports should be use, please?