chiseltest
chiseltest copied to clipboard
ucb-bar
The batteries-included testing and formal verification library for Chisel-based RTL designs.
The 'reset' signal cannot glitch from 0 to 1 at power on. If it does, then all the assertions in a vcs design will fire.
Updates [org.scalatest:scalatest](https://github.com/scalatest/scalatest) from 3.2.12 to 3.2.13. [GitHub Release Notes](https://github.com/scalatest/scalatest/releases/tag/release-3.2.13) - [Version Diff](https://github.com/scalatest/scalatest/compare/release-3.2.12...release-3.2.13) I'll automatically update this PR to resolve conflicts as long as you don't change it yourself. If you'd...
The overall goal is to be able to run chiseltest unit tests with `CIRCT`/`firtool` *instead* of `firrtl` ## This is first step. It does the following - Creates a new...
I am using empty Decoupled interfaces which is just a ready/valid signal to synchronize modules. A very simple and convenient feature would be to have a enqueueEmpty and expectDequeueEmpty methods...
When finishing a test, the very last updates to signals are very hard to identify in the VCD file, as shown in the screenshot attached. While rdData, dmaNum and pktLen...
Example of multi-clock circuits: https://github.com/edwardcwang/chisel-multiclock-demo It would make testing these kinds of circuits more DRY and less tedious than manually creating a wrapper Module. Ideas * testers1 semantics (poke-clock and...
