Simulation is timing out

[Rahul-Kande]

Hi, I am trying to setup the rocket-chip processor using the Chipyard framework. I want to simulate the rocket chip using the Synopsys VCS simulator. I am able to compile the hardware and simulate it, but the simulation times out and the output trace file is not reflecting the instructions I want it to run. I am attaching the dump of input file I used and the trace file I got as output. The following are the instructions I followed for setup. Please let me know if you have any suggestions to resolve the issue.

• I installed the dependencies listed here: https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/Initial-Repo-Setup.html

• git clone https://github.com/ucb-bar/chipyard.git cd chipyard ./scripts/init-submodules-no-riscv-tools.sh ./scripts/build-toolchains.sh riscv-tools --ignore-qemu source ./env.sh

• cd sims/vcs make CONFIG=TinyRocketConfig

• this is the command I used for simulation: simv-chipyard-TinyRocketConfig +permissive -cm "line+cond+fsm+tgl+branch+assert" +dramsim +dramsim_ini_dir=/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +ntb_random_seed_automatic +verbose +permissive-off ../../tests/hello.riscv

hello.dump.txt my_trace_1.log.zip