What I need to write a TileLink DDR controller?

[siyy123]

I'm trying to write a TileLink DDR controller to replace the default AXI4 memory port. So what I need to write a TileLink DDR controller?

[alonamid]

AFAIK, a DDR controller is a non-trivial endeavor, but we will be happy to accept a PR for a DDR controller which connects to the Tilelink memory bus.