Chisel 7 Bump Issue due to Default Layers

[seldridge]

FYI: if this project tries to bump to Chisel 7, which now includes default layers, there will be problems with how the FMATester.scala generates Verilog here: https://github.com/ucb-bar/berkeley-hardfloat/blob/26f00d00c3f3f57480065e02bfcfde3d3b41ec51/hardfloat/tests/src/FMATester.scala#L61

With default layers always being there, then doing this may create an invalid single-file Verilog file that has `include directives pointing at directories/files which don't exist.

This can either be fixed by changing the ChiselStage invocation to include -enable-layers arguments that specialize away the default layers or this invocation could be changed to use one-file-per-module output and changing the Verilator invocation to properly setup +incdir pointing at the output directory.

[nibrunieAtSi5]

Thanks for the heads-up @seldridge