Martin Troiber
Martin Troiber
Testing required: How does the `sys_clk` speed in `litex_sim.py` affect the responsiveness of the simulation?
@suarezvictor I found walking through the litex fpga-101 the best resource when initially getting started: https://github.com/litex-hub/fpga_101 Also +1 for the Migen/nMigen confusion. Guess I never used nMigen then...
Did you create the `demo.bin` with this command: `litex_bare_metal_demo --build-path=build/sim`? If you use the prebuilt `demo.bin` then it might be based on the wrong `csr.csv` file. I just tried reproducing...
@dhftah Do you think we could take the Frame related changes from https://github.com/grafana/grafana/compare/main...dhftah:frk.grafana:fix-openapi-specification and already make PR out of them?
@aignacio I just tried reproducing your build but I ran into a seemingly simple error when running the `make` command: ``` make make: *** No rule to make target 'fpga.bit',...
Thanks so much! :tada:
I think some `vstart` related tests would also be helpful. So far my ISA simulator always set `vstart` to zero which should lead to issues I think but there are...
Did you already make any progress on this issue? For now I resorted to rendering to a virtual framebuffer using `Xvfb`. The performance is really promising (close to 2x the...
@jerryz123 Regardless of how they want to integrate these changes in Spike, I'll try to put together an update PR in this repo over the weekend.