risc topic
8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
mrisc32
MRSIC32 ISA documentation and development
RISVM
A low overhead, embeddable bytecode virtual machine in C++
mrisc32-a1
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
FPGACosmacELF
A re-creation of a Cosmac ELF computer, Coded in SpinalHDL
platform-shakti
Shakti: development platform for PlatformIO
sharedsignals
OpenID Shared Signals Working Group Repository
Plotty
C language compiler from scratch for a custom architecture, with virtual machine and all
croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.