risc topic

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

liuqdev

MRSIC32 ISA documentation and development

mrisc32

A low overhead, embeddable bytecode virtual machine in C++

bitmario

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

mrisc32

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

wel97459

Project Oberon RISC emulator in Go

fzipp

Shakti: development platform for PlatformIO

platformio

OpenID Shared Signals Working Group Repository

openid

C language compiler from scratch for a custom architecture, with virtual machine and all

SuperJMN

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

ben-marshall