computer-architecture topic
wwcsf-backend-study-group
WWCode Backend Study Group
Verilog-Snippets
Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
e16-co502-RV32IM-pipeline-implementation-group1
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 inst...
algebraic-nnhw
AI acceleration using matrix multiplication with half the multiplications
CNN-ACCELERATOR
Hardware accelerator for convolutional neural networks
archsim
A survey on architectural simulators focused on CPU caches.
Cache-Simulator
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of refe...
Artificial-Intelligence-in-Compiler-Optimization
A curated list of research papers, datasets, and tools for applying machine learning/Deep learning techniques to compilers and program optimization.
FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
awesome-linux-kernel
Useful resources for learning kernel