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cadence-virtuoso repositories
Analog-Design-of-Asynchronous-SAR-ADC
115
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18
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This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
cdsdm
32
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11
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Cadence Virtuoso Design Management System
RF-design-of-1.9-GHz-Rx-frontend
21
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3
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This project shows the design process of the main blocks of a typical RX frontend system.
Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
17
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7
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This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
Cadence_Virtuoso_180nm_Projects
16
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2
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Schematic, Layout Design & Simulation in 180nm Technology