⚙Hardware Synthesis Laboratory Using Verilog
module rom( output reg [7:0] data, input wire [7:0] addr, input wire clk ); parameter width = 8; parameter bits = 5; reg [width-1:0] rom [2**bits-1:0]; initial $readmemb("rom.data", rom); always@(posedge clk) begin data <= rom[addr]; end endmodule
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