Tom Roberts comments

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                                            Tom Roberts

Violation of the Data Independent Timing property for misaligned Load and Store Instructions

Agreed - it should be a stipulation on SW to avoid any unaligned accesses in regions of code where this security property is required. We can't arbitrarily perform extra memory...

Violation of the Data Independent Timing property for misaligned Load and Store Instructions

Thanks again for this report and the input on proposed solutions. For now, I have added #1455 to update the documentation. We don't want to increase the verification space by...

Verifying instruction memory faults with the ICache

Yep that looks correct, and kind of what I was getting at with the comment [here](https://github.com/lowRISC/ibex/pull/1435#discussion_r713073318) When I've done this before, we did the static approach (a particular address will...

[dv] riscv_pmp_out_of_bounds_test fails with sim mismatch

This looks to be the same root cause as #1165 (random addresses are chosen for load/store access sequences and some of those addresses hit memory regions that cause access exceptions...

Enable a way to configure the Cache characteristics from the Ibex Core Top

A lot of the parameters in the I$ are fairly specific - but it seems reasonable to expose the cache size at the top level. I'll re-open this issue to...