Tej Sanghavi

Results 2 issues of Tej Sanghavi

**Describe the bug** `Begin` and `end` keywords are required to be enclosed around `always_comb` process blocks for an image to be generated. **To Reproduce** See diff: https://github.com/tms4517/Yosys_to_aid_with_RTL_design/commit/5bc1960aa5e5cca50ef6a6118e27ffb84f7c490f **Screenshots** Without: ![image](https://github.com/TerosTechnology/vscode-terosHDL/assets/41344492/d68cef7a-a61c-4959-9fb9-326647c04867)...

bug
documenter

**Describe the bug** The conditional operator is not supported. For an image to be generated, replace ?, with if else statements. **To Reproduce** See diff: https://github.com/tms4517/Yosys_to_aid_with_RTL_design/commit/57cfb14fc4e5f5aef2e1236bc8f05f0a9d4fe48f **Please complete the following...

bug
documenter