T. Meissner

> vunits aren't yet supported outside synthesis. Oh, in that case I will add a hint to the PSL documentation. The current PSL doc could be the cause that people...

I've updated the [documentation](https://ghdl.readthedocs.io/en/latest/using/ImplementationOfVHDL.html#psl-vunit-files-vhdl-2008-synthesis-only) with information about that vunits are only supported with VHDL-08 & synthesis. See commit 5a5419c.

Okay, I tried the mcode backend. ``` $ ghdl --version GHDL 5.0.0-dev (4.1.0.r110.g918a63daf) [Dunoon edition] Compiled with GNAT Version: 10.5.0 static elaboration, mcode JIT code generator Written by Tristan Gingold....

I assume that the error occurs because of you are trying to synthesize a multi-clock FF, which is not supported by yosys. See #127 for a similar issue.

`Inout` ports of record types don't work with VHDL (pre VHDL-2019) synthesis. You have to split your record in two, one for each direction. This isn't a GHDL limitation, it's...

I think VHDL `std_logic_vector` also "maps" on PSL `bitvector`, so it should be legal. AFAIR I had this discussion with Tristan already during testing or implementing PSL stuff in GHDL....

PSL standard (IEEE 1850-2010): **5.1.2:** > In VHDL, type STD.Standard.Bit, and type IEEE.Std_Logic_1164.std_ulogic, as well as subtypes thereof, are Bit types. **5.1.3:** > In VHDL and GDL, any type that...

> I maybe was not precise: > > * PSL `BitVector` definitely maps to `std_logic_vector`. > > * PSL `BitVector` does not map to `std_logic` and IMHO should return the...

That would also interesting for me. Some years ago I had an own OSVVM branch implementing XML exports which were further processed with Python scripts.

@lainy If you try your example above in Modelsim for example, it will work. But it will run very very slow. I have similar properties in internal protocol checkers and...