Marek Materzok
Marek Materzok
Instructions per cycle (IPC) are if-bigger-then-better. So is maximum synthesis frequency (Fmax). LCs are if-smaller-then-better (less FPGA resources used). > Is it OK to create a dict indicating so directly...
This turned out to not to be a bug, but rather an unexpected change of behavior. We used `Simulator.run_until` to implement timeouts in tests. The previous default behavior (`run_passive ==...
I'll do something like that. Thanks. And I'll use this opportunity to thank you and your team for the great work. Thanks to the various improvements, some of our code...
> Approved, but I have mixed feelings about this PR. I don't like the fact that RS is reordering ids so that WakeupSelect can choose first one. This break an...
> Hit a slight issue, as synthesizing gave the following error: (...) I believe multiple driver error shouldn't happen with Amaranth, so this looks like an Amaranth/Yosys problem. You changed...
Nice improvement!
> yeah, it is, but I expected it to be bigger (hope that's not a wishful thinking). Did you have any expectations of it? Also hoped for a bigger difference,...
Given that benchmarks and other full core tests work fine, most probably the issue is related to M-mode and interrupt handling. Indeed RISCV-DV claims to cover this.
Test failing because of the time limit - increase timeout on `run-regression-tests` workflow.
Add PMP tests.