threewholefish

I'm interested in generating parsers/generators in Verilog/SystemVerilog, which would be used as one endpoint with the existing C/C++ implementations as the other. I've used [Jinja](https://jinja.palletsprojects.com/en/3.1.x/) for code generation in previous...

Further to this, I think that any information in an `INFO` line should be short and sweet, and the full details of the frame reserved for `DEBUG`. IMO, RX and...