Sioni Summers

Hi, thanks for looking at this. My thoughts: - I agree we don't need the writer flow in the `requires`, since it's the model with modified FIFO depths that we...

Hi, this issue is Vivado version related. I think it works on 2018 versions, but this error appears for 2019 and 2020 versions. I haven't figured out what actually causes...

Would you be able to test [this branch](https://github.com/thesps/conifer/tree/pipeline)? It contains PR #12 , which should resolve that `Abnormal program termination` error for older Vivado versions as well as support Vitis.

Thanks for the comments, and the PR, I've merged it! On Error 1, did you `pip install .` in the root directory of the project? That should make the package...

Hi, these examples are not at all optimized in terms of the precision used, which can have an effect on numerical accuracy. Did you try any tuning?

Hi, in this case I would recommend using the VHDL backend, if possible. The long synthesis time with the HLS is an issue that we don't have a solution for...

We still need some manual component to the action, just a click button or anything to trigger the making of the branch. That’s just to have some oversight to prevent...

What about the interplay with `VivadoAccelerator` backend? The IPs generated from Vitis HLS should be perfectly compatible with those block designs, and it would be good to take advantage of...

Hi, right now there is nothing like the 'VivadoAccelerator' backend from hls4ml for conifer. I intend to make an interface to use hls4ml's AXI interface and scripts from conifer, but...

There's an implementation of bitstream generation at #53 . ZCU104 is there in the supported boards. I don't have a ZCU104 to test on but I was able to make...