Bitstream generation feature

[AnouarITI]

Hello,

I am trying to generate a bitstream directly for the ZCU104. However, when I checked the generated HLS project found out that: 1- There is no AXI bridge. 2- there is no TCL script to generate the bitstream. I thought because I am using the Xilinxhls backend, but it seems this is the same case for the other backend.

Sould make this manually, Or I missed something here?

[thesps]

Hi, right now there is nothing like the 'VivadoAccelerator' backend from hls4ml for conifer. I intend to make an interface to use hls4ml's AXI interface and scripts from conifer, but it's not done yet.

If you are okay to manipulate the HLS and work with Xilinx tools yourself, you can use the AXI template and scripts from hls4ml with a conifer model, just replacing the function call to the model in the AXI wrapper HLS function.

There is also the 'FPU' backend of conifer that might be useful for you, depending on the deployment use case. I haven't added ZCU104 support for it yet but it should not be too difficult. This is a different usage mode of the tool, that you make one IP/bitfile without a specific model, then program a trained model onto it later.

There's more information on the FPU here.

[thesps]

There's an implementation of bitstream generation at #53 . ZCU104 is there in the supported boards. I don't have a ZCU104 to test on but I was able to make a bitstream. (I've tested bitstreams on other devices). Check the new hls_accelerator.py example to see how to use it

[thesps]

FYI I have built an FPU bitstream for zcu104 and put it on the downloads page at https://ssummers.web.cern.ch/conifer/downloads/dev/zcu104/

Take a look at the quickstart guide usage here for the code you should run on the zcu104 software side using Xilinx's pynq package: https://ssummers.web.cern.ch/conifer/fpu.html#quickstart You should just change AlveoDriver to ZynqDriver