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Unit testing for cocotb

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**Problem:** * The current framework enforces a compilation order between VHDL and Verilog sources (e.g. in the case of the Questa simulator, all VHDL sources are compiled before Verilog). This...

### Problem The specific issue I am having is that fsdb dumping cannot be done if Verdi is not installed or linked to VCS. I am running VCS (S-2021.09) on...

Hi, I get the following error when running verilator, any idea what could be causing this? Previously I have run similar tests without issues ``` Entering directory '/mnt/D/d/count/sim_build' g++ verilator.o...

question

Verilator requires string parameters to be surrounded by quotes: `-Gparam="value"` > Strings > > Strings must be in double quotes (“”). They must be escaped properly on the command line,...

…compilation. I'm running verilator on a large design and the compilation was taking a long time. I wanted to able to call 'make -j 16' to speed things up, but...

I'm trying to integrate cocotb-test into a [verification GUI](https://github.com/Eideticom/hdl-verifgui/tree/david/cocotb) I'm writing, and would like better options for runtime management of tests. Specifically, I need to support two use cases: -...

Not sure if this is by design or not, but it took me a while to track down why `vsim` was not accepting my `sim_args`. It looks like you escape...

Using pytest-xdist or pytest-parallel would not work with single generated **simv**. Specifying a different **work_dir** does not seem to work either. Having a way to separate VCS runs (output to...

Hi, could you please remove the default argument "-elaborate" on Xcelium/Ius simulator, to use that you need to force work lib creation previously, what doesn't happen at time 0 when...

Allow the python logs to go to a file and console at the same time. Used the logging.config.dictConfig() to configure the loggers with two handlers: ->console output using logging.StreamHandler ->file...