synth_opt_adders
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tdene
Prefix tree adder space exploration library
Need to: * [ ] Use Verilator to lint HDL * [ ] Use Verilator to simulate * [ ] Perform language equivalence checking * [ ] Perform logic equivalence...
Currently, the docstrings in this repo fail pydocstyle consistently. This should be fixed.
It would be good to be able to use Yosys's formal equivalence checking functionality to check that various forms of the adders are actually equivalent.
Adds onto #18 and #23 Is related to, and possibly a subset, of #28 Need to: * Check syntactic validity of generated VHDL code with GHDL * Lint generated VHDL...